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d a t a sh eet product speci?cation supersedes data of december 1994 file under integrated circuits, ic01 1995 jul 17 integrated circuits TDA1315h digital audio input/output circuit (daio)
1995 jul 17 2 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h features transceiver for spdif and iec 958 encoded signals high sensitivity input for transformer-coupled links ttl-level input for optical links built-in iec input selector built-in iec feed-through function automatic sample frequency (f s ) detection system clock recovery from iec input signal low system clock drift when iec input signal is removed error detection and concealment pll lock detection in transmit mode serial audio interface conforms to i 2 s-bus format auxiliary i 2 s-bus input for analog-to-digital converter (adc) audio output selector microcontroller-controlled and stand-alone mode 128-byte buffer for user data bytewise exchange of user data with microcontroller decoding of compact disc (cd) subcode q-channel data support for serial copy management system (scms) light emitting diode (led) drive capability (sample frequency and error indication) pin-selectable device address for microcontroller interface power-down mode. general description the digital audio input/output circuit (daio) of the TDA1315h is a complete transceiver for biphase-mark encoded digital audio signals that conform to the spdif and iec 958 interface standards (consumer mode), made in the full cmos-process c200. in the receive mode, the device adjusts automatically to one of the three standardized sample frequencies (32, 44.1 or 48 khz), decodes the input signal and separates audio and control data. a clock signal of either 256 or 384 times the sample frequency is generated to serve as a master clock signal in digital audio systems. in the transmit mode, the device multiplexes the audio control and user data and encodes it for subsequent transmission via a cable or optical link. ordering information type number package name pin position version TDA1315h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
1995 jul 17 3 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h quick reference data all inputs are ttl compatible; all outputs are cmos compatible; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage v ddd =v dda 3.4 5.0 5.5 v i ddaq analog quiescent current pd = 1; t amb =25 c -- 10 m a i dddq digital quiescent current pd = 1; t amb =25 c -- 10 m a i dda analog supply current f s = 48 khz; clksel = 0; when iecin1 input is used - 2.6 - ma i ddd digital supply current f s = 48 khz; clksel = 0 - 13 - ma power p tot total power dissipation f s = 48 khz; clksel = 0; when iecin1 input is used - 80 - mw temperature t amb operating ambient temperature - 20 - +70 c iec interface; pin iecin1 (high sensitivity iec input) v i(p-p) ac input voltage (peak-to-peak value) 0.2 - v dd v control part chmode, unlock, fs32, fs44, fs48 and copy ( open - drain outputs ) v ol low level output voltage i ol = 3 ma -- 0.5 v reset, sck, lclk, lmode and sysclki ( hysteresis inputs ) v thl negative-going threshold v dd = 4.5 to 5.5 v 0.6 -- v v tlh positive-going threshold v dd = 4.5 to 5.5 v -- 2.4 v v hys input voltage hysteresis v dd = 4.5 to 5.5 v - 0.7 - v clock and timing v ref output reference voltage - 2.1 - v rc int ( pin 44) i chfr charge-pump output current frequency detector loop - 12 -m a i chph charge-pump output current phase detector loop - 24 -m a
1995 jul 17 4 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h block diagram fig.1 block diagram.
1995 jul 17 5 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h pinning symbol pin padcell description rc ?l 1 e029 pll loop ?lter input v ref 2 e029 decoupling internal reference voltage output v dda 3 e008 analog supply voltage v ssa 4 e004 analog ground iecin1 5 e007 high sensitivity iec input iecin0 6 ipp04 ttl level iec input iecsel 7 iup04 select iec input 0 or 1 (0 = iecin0; 1 = iecin1); this input has an internal pull-up resistor ieco 8 opfh3 digital audio output for optical and transformer link iecoen 9 iup04 digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an internal pull-up resistor testb 10 ipp04 enable factory test input (0 = normal application; 1 = scan mode) testc 11 ipp04 enable factory test input (0 = normal application; 1 = observation outputs) unlock 12 opp41a pll out-of-lock (0 = not locked; 1 = locked); this output can drive an led fs32 13 opp41a indicates sample frequency = 32 khz (active low); this output can drive an led fs44 14 opp41a indicates sample frequency = 44.1 khz (active low); this output can drive an led fs48 15 opp41a indicates sample frequency = 48 khz (active low); this output can drive an led chmode 16 opp41a use of channel status block (0 = professional use; 1 = consumer use); this output can drive an led v ddd2 17 e008 digital supply voltage 2 v ssd2 18 e009 digital ground 2 reset 19 idp09 initialization after power-on, requires only an external capacitor connected to v ddd ; this is a schmitt-trigger input with an internal pull-down resistor pd 20 ipp04 enable power-down input in the standby mode (0 = normal application; 1 = standby mode) ctrlmode 21 iup04 select microcontroller/stand-alone mode (0 = microcontroller; 1 = stand-alone); this input has an internal pull-up resistor laddr 22 ipp04 microcontroller interface address switch input (0 = 000001; 1 = 000010) lmode 23 ipp09 microcontroller interface mode line input lclk 24 ipp09 microcontroller interface clock line input ldata 25 iof24 microcontroller interface data line input/output strobe 26 idp04 strobe for control register (active high); this input has an internal pull-down resistor udavail 27 opf23 synchronization for output user data (0 = data available; 1 = no data) testa 28 ipp04 enable factory (scan) test input (0 = normal application; 1 = test clock enable) copy 29 opp41a copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output can drive an led invalid 30 iod24 validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin has an internal pull-down resistor deem 31 opf23 pre-emphasis output bit (0 = no pre-emphasis; 1 = pre-emphasis) mute 32 iup04 audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an internal pull-up resistor
1995 jul 17 6 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h i 2 ssel 33 iup04 select auxiliary input or normal input in transmit mode sdaux 34 ipp04 auxiliary serial data input; i 2 s-bus sd 35 iof24 serial audio data input/output; i 2 s-bus ws 36 iof24 word select input/output; i 2 s-bus sck 37 iof29 serial audio clock input/output; i 2 s-bus i 2 soen 38 iup04 serial audio output enable (0 = enabled; 1 = disabled/3-state); this input has an internal pull-up resistor sysclki 39 ipp09 system clock input (transmit mode) sysclko 40 opfa3 system clock output (receive mode) v ssd1 41 e009 digital ground 1 v ddd1 42 e008 digital supply voltage 1 clksel 43 iup04 select system clock (0 = 384f s ; 1 = 256f s ); this input has an internal pull-up resistor rc int 44 e029 integrating capacitor output symbol pin padcell description fig.2 pin configuration.
1995 jul 17 7 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h functional description modes of operation with respect to the control of the device and the exchange of non-audio data, a microcontroller (host) mode and a stand-alone mode can be considered. the selection of the mode is performed at pin ctrlmode. in the stand-alone mode, the device configuration is solely determined by pins. in the host mode an internal control register, or pins or both can be used to change the default settings. with respect to the direction of the digital audio data, the device can be operated in either a transmit or a receive mode under control of a microcontroller. in the stand-alone mode the device is only a receiver. in the receive mode the input signal can also be made available at the output pin ieco (feed-through) to ease the cascading of digital audio equipment. the device can be brought to standby mode at all times by activating the pd pin (power down). in this mode all functions are disabled, all outputs 3-stated, supply current is minimized and the contents of the register are saved. general for those applications where it is important to save power, the pd pin is provided, which, when activated, puts the TDA1315h in standby mode by disabling all functions and 3-stating all outputs, while saving register contents. as illustrated in fig.1, the TDA1315h contains the following major functional blocks: iec input section biphase demodulator frame and error detection clock and timing section iec output section biphase modulator audio section (i 2 s-bus transceiver) non-audio section (control and fifo) user (microcontroller) interface. iec input section there are two biphase signal inputs to the iec input section. iecin0 accepts ttl levels from, for example, an optical input device, while iecin1 is designed for coaxial cable inputs and requires signal levels of minimum 200 mv (p-p) via an external coupling capacitor. the selection of the active input channel is performed by pin iecsel or by the control register or both. in the receive mode, the selected input signal is applied internally to the biphase audio output section to enable a feed-through function. b iphase demodulator in the biphase demodulator, the received signal (for details see chapter references[1] and [2]) is converted to binary data and separated into audio and non-audio data for further processing in their dedicated sections. the demodulated input signal is also required for frame and error detection. f rame and error detection in the frame and error detection block, the framing information from the received biphase signal is retrieved to synchronize the biphase demodulator and to allow access to the audio and non-audio data bits. an out-of-lock condition of the pll is flagged at unlock. the validity of audio samples is indicated at pin invalid. c lock and timing section in the clock and timing section, the timing information inherent to the received biphase signal is retrieved and a symmetrical master clock signal is generated and output at pin sysclko. depending on the mode of operation, the frequency of this master clock can be selected by pin clksel, by the control register or both to be either 256f s or 384f s (f s = audio sampling frequency). this section contains all the circuitry of a phase-locked loop (pll), except for the loop filter components, which are connected externally to pins rc int and rc fil . when the input signal is interrupted, the oscillator will slowly drift to the centre frequency in order to keep the system operating on a proper frequency. in the transmit mode, all required timing signals are input at pin sysclki and are derived from an externally supplied system clock of either 256f s or 384f s . the input high time of that clock may be in the range between 30% to 70% of the clock period. iec output section in the iec output section, either the received (feed-through function) or the generated biphase signal is selected for output at pin ieco, depending on the receive/transmit mode. the output can be enabled/disabled by pin iecoen, by the control register or both, and can drive a suitable optocoupler and a transformer in parallel.
1995 jul 17 8 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h b iphase demodulator in the biphase modulator section, audio and non-audio data are combined into subframes, frames and blocks, and encoded in the biphase-mark format during transmit mode. although there are always 24 audio bits per sample in a subframe, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register (host mode). a udio section in the audio section, the left and right channel audio samples are taken from the demodulated data frames and are output serially in accordance with the i 2 s-bus format (for details see chapter references[3] pins sd, sck and ws) when the TDA1315h is in the receive mode (i 2 s-bus transmitter). the audio output signals are concealed or muted in case certain errors were detected during reception. mute can be enforced by pin mute or via the control register (host mode) and affects, depending on the receive/transmit mode, the i 2 s-bus or iec output signals. mute is internally synchronized with the audio data. in the transmit mode, there is an additional i 2 s-bus data input sdaux made available to accept audio data from, for example, an adc. this input can be selected either by pin i 2 ssel, by the control register or both. the i 2 s-bus port can be enabled/disabled by pin i 2 soen, by the control register or both. in the transmit mode, i 2 s-bus data and timing are supplied by an external source, the TDA1315h then becomes an i 2 s-bus receiver. in this event, selection of an i 2 s-bus source determines which signal is to be output at ieco. although the phase relationship between system clock (sysclki) and i 2 s timing (sck) is not critical they must be synchronous with each other, i.e. be derived from the same source. receive mode the iec subframe format defines 20 bits for an audio sample, plus 4 auxiliary bits, which can be used to extend the word length. by default, all 24 data bits per sample are output via the i 2 s-bus port. this can be changed, however, to 16, 18 or 20 bits via bits 2 and 3 in byte 1 of the control register. the remaining bits will then be zero. the serial audio clock frequency at pin sck is 64 f s , i.e. there are 32 clock pulses per audio sample (left or right channel). apart from detecting the out-of-lock condition of the pll, received data is checked for the errors listed below. all detected errors will be flagged in the status register and two of them brought out to a pin. depending on the type of error, different measures are taken. validity flag set. this error condition is also output at pin invalid, simultaneously with the data. the corresponding audio sample is not modified. parity check error. a concealment operation is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. biphase violation (other than preambles). a concealment operation (hold) is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. pll is out-of-lock. this error condition is also output at pin unlock. both audio output channels (left and right) are set to zero (mute). the error condition is sampled with the high-to-low transition of ws, i.e. muting becomes effective when the outputting of a stereo sample begins. when the pll has locked again, muting is released only after a full block of audio samples has been received, free of errors.the invalid output will always be set to low simultaneously with this muting. in the receive mode it is possible to select the auxiliary i 2 s-bus data input sdaux for output at pin sd. however, there will be no suitable system clock available in the event of an open iec input or a disabled iec source and output sd will be muted when the TDA1315h is not in lock. regardless of which source is selected, a mute command will always mute the output signal at pin sd and set the invalid output to low regardless of the validity bit value. when mute command is disabled, muting will be released when the outputting of the next stereo sample begins.
1995 jul 17 9 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h table 1 summary of validity and muting in the receive mode note 1. x = dont care. input conditions (1) outputs pll locked mute activated sdaux selected i 2 sout enabled validity bit invalid sd x x x no x 3-state 3-state no x x yes x 0 0 x yes x yes x 0 0 yes no no yes 0 0 iec yes no no yes 1 1 iec yes no yes yes x 0 sdaux when the i 2 s-bus output port is disabled by pin i 2 soen in the stand-alone mode, pins ws, sck, sd and invalid will immediately become 3-state. if, however, this is performed in the host mode via the i 2 soen pin or the corresponding bit in the control register, only sd and invalid will become 3-state immediately. pins ws and sck will only become 3-state after the rising edge of strobe when the strobe pulse changes the setting from receive to transmit mode. thus in the host mode, when remaining in the receive mode, i 2 soen only influences the sd and invalid pins. pins ws and sck are always enabled. when the i 2 s-bus output port is re-enabled, data output will start with the beginning of a new stereo sample. transmit mode although the iec subframe format supports up to 24 bits per audio sample, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register. because the i 2 s-bus port then operates as a receiver, the timing has to be selected so that all data bits can be received. any bits unused or unsupplied will be set to logic 0. the information regarding audio samples that may be unreliable or invalid has to be entered at pin invalid simultaneously with the data input to pin sd. the timing will be the same as in the cd decoder ics (e.g. the efab signal of the saa7310, see chapter references[5]. as the i 2 s-bus port is used as an input, it must be disabled by the correct combination of pin i 2 soen and the corresponding bit in the control register. the pins ws and sck are set to 3-state on the rising edge of strobe, whenever the transmit mode is activated. i 2 soen influences only the data pin sd. this allows for three different configurations: transmit mode #1, i 2 soen = 1, i 2 ssel = 1. in this instance, i 2 s-bus timing and data are derived from an external source and entered at pins ws, sck and sd. output will be at pin ieco, if iecoen permits. transmit mode #2, i 2 soen = 1, i 2 ssel = 0. in this instance, i 2 s-bus timing is derived from an external source and entered at pins ws and sck and is also supplied to another i 2 s-bus source, such as an adc. data from that other i 2 s-bus source is entered at pin sdaux. output will be at pin ieco, if iecoen permits. in this instance, i 2 ssel acts as a source selector for pins sd and sdaux. transmit mode #3, i 2 soen = 0, i 2 ssel = 0. in this instance, i 2 s-bus timing is derived from an external source and entered at pins ws and sck and is also supplied to another i 2 s-bus source, such as an adc. data from the other i 2 s-bus source is entered at pin sdaux. output will be at pin ieco, if iecoen permits, and at pin sd. in this mode, sdaux data is available both at the iec output (a type of digital monitor function) and on the i 2 s-bus (e.g. for digital signal processing purposes). the remaining combination (i 2 soen = 0, i 2 ssel = 1) is not used. ws, sck and sd are then 3-state. because the sdaux input normally receives a signal from an adc, the signal at pin invalid will not be interpreted when this input is selected. all samples are assumed to be valid. in all transmit modes, invalid is an input pin.
1995 jul 17 10 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h whenever mute is activated in any of the transmit modes, the audio data of the iec output signal will be muted and the validity bit set to logic 0, regardless of the invalid input value. when sdaux is selected, mute will also affect the output at pin sd. table 2 summary of validity and muting in the transmit mode note 1. x = dont care. input conditions (1) iec output signal mute activated sdaux selected invalid input validity bit audio bits no no 0 0 from sd no no 1 1 from sd no yes x 0 from sdaux yes x x 0 0 n on - audio section in the non-audio section, the first 30 channel status bits are taken from each block of data. a selection of 16 bits is then assembled as two bytes and transferred to the user interface. in the event of an incorrect iec signal, i.e. no consumer mode, an error will be flagged at pin chmode. the error signal will return to its passive state after a full block of consumer mode data has been received. the user data bits are searched for the beginning of a message (see section user data), which is then stored bytewise in a buffer that can be read by an external microcontroller via the user interface. in the transmit mode, channel status and user data bits are taken from an internal buffer that has been written to by an external microcontroller via the user interface. these bits are required for frame composition in the biphase modulator. the non-audio section supports only the consumer mode of the iec 958 specification and handles the channel status and user data information. the non-audio section can be operated in the stand-alone mode (receive only) and the host mode (transmit/receive). in the stand-alone mode, a few bits from the channel status are brought out to pins, the user data is not available. in the host mode, channel status and user data are exchanged using a microcontroller. after a reset in the host mode, the TDA1315h provides general format by default. channel status the channel status consists of 30 bits, a number of which are reserved for future standardization. the 16 most significant bits (msbs), arranged as two bytes, are exchanged using an external microcontroller. the mapping of the channel status bits into these two bytes is given in tables 3 and 4. all scms operations (serial copy management system) will be performed in the microcontroller and no manipulation in the TDA1315h is possible. bit 0 is always the first bit on the user interface. in the receive mode, an error signal is generated at pin chmode if a professional mode signal is received. even then, two bytes of information, mapped as defined in tables 3 and 4, are generated for output. although there are two bytes of channel status available for output, only the first byte can be read. to identify future modes of the channel status, both mode bits (bits 6 and 7 in the channel status) are available (inverted) from the TDA1315h status register. the channel status is created from the left channel subframes of the iec signal (preambles b and m). whenever the channel status, as defined in tables 3 and 4 (16 bits), differs from the previously received channel status, a bit will be set in the TDA1315h status register. this helps to reduce the data traffic by enabling the microcontroller to read the channel status only after it has changed. in the transmit mode, the microcontroller supplies consumer mode (mode 0) channel status data as described in table 3. both bytes need to be transferred.
1995 jul 17 11 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h table 3 first byte of transferred channel status table 4 second byte of transferred channel status user data in principle, the user data bits may be used in any way required by the user. in order to guarantee compatibility between signals of any source, attempts have been made for the standardization of a user data format. the basic idea is to transfer messages that consist of information units. as messages are, typically, asynchronous with the iec audio block structure, their transfer relies on software protocol. currently, the applications for cd subcode and dat have been accepted. their general format complies with that protocol and can be described as follows: user data is transferred in the form of messages. messages consist of information units, i.e. groups of 8 bits (bytes). messages are separated by more than 8 zero bits (0). information units within a message may be separated by 0 up to and including 8 zero bits. the msb of each byte is sent first in the user data channel. the msb of each byte is a 1-bit (1, start bit). for cd subcode, one byte consists of bits 1qrstuvw. bit description bit in channel status 0 and 1 clock accuracy 29 and 28 2 and 3 sample frequency 25 and 24 4 pre-emphasis 3 5 copyright 2 6 audio/data 1 7 consumer/professional use 0 bit description bit in channel status 0 category code 15 1 category code 14 2 category code 13 3 category code 12 4 category code 11 5 category code 10 6 category code 9 7 category code 8 normally, the exchange of user data between the TDA1315h and the microcontroller is based on the general format described above. in the event of cd subcode, this means that 96 bytes need to be transferred for each subcode frame. in order to reduce the amount of data traffic, it is possible to separate the q-channel bits from the user data and transfer only them. this mode can be enabled by a bit in the control register and leads to the transfers of only 12 bytes per subcode frame. as there is no check in the TDA1315h whether user data is from a cd source, this q-channel decoding can be employed whenever the user data format permits. receive mode user data bits are extracted from the received iec subframes and searched for the beginning of a message. when q-channel decoding is disabled (in the control register), the data bytes of a message are stored in a buffer for subsequent external interpretation or processing. any 0 bits between information units and between messages are skipped. it is essential to maintain synchronization of messages, even if not all bytes of a message can be exchanged with the microcontroller in a single transfer, or if there are several messages in the buffer. when user data is transferred in the general format described earlier, the beginning of a message is indicated in the buffer by a 1 bit in the msb position of the first byte of that message. in all subsequent bytes of the same message, the msb will be zero. this is illustrated in table 5 for the cd subcode. the user data buffer is implemented as a fifo (first-in, first-out) with a size of 128 bytes. this allows the storing of a full cd subcode frame. a synchronization signal at pin udavail supports the transfer of user data to the microcontroller. this signal goes low when there is at least 1 byte of user data in the buffer, and returns high only after the last received byte has been read. this is illustrated in fig.3. based on the timing of the cd subcode, the microcontroller should start reading data within 17 ms after udavail has gone low, otherwise the buffer will fill completely and the most recent data will be lost.
1995 jul 17 12 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h table 5 synchronization of user data msb user data lsb function 0.............. - 1 q1 r1 s1 t1 u1 v1 w1 start of message 0 q2r2s2t2u2v2w2 - 0 q3r3s3t3u3v3w3 - 0.............. - 0.............. - 0 q95 r95 s95 t95 u95 v95 w95 - 0 q96 r96 s96 t96 u96 v96 w96 - 1 q1 r1 s1 t1 u1 v1 w1 start of next message 0 q2r2s2t2u2v2w2 - 0 q3r3s3t3u3v3w3 - 0.............. - although the msb is first within the iec user data channel, the lsb is sent first on the user interface to be compatible with other data, i.e. the first byte of a subcode user data frame will be output as follows: 1. bit sent = w1. 2. bit sent = v1. 3. bit sent = u1. 4. bit sent = t1. 5. bit sent = s1. 6. bit sent = r1. 7. bit sent = q1. 8. bit sent = 1. when q-channel decoding is enabled, only the q-channel bits are taken from the user data frame and stored in the buffer. again, any separating 0 bits are skipped. table 6 shows how data is arranged in the buffer. table 6 layout of q-channel data msb user data lsb .. .. .. .. .. .. .. .. q89 q90 q91 q92 q93 q94 q95 q96 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. q89 q90 q91 q92 q93 q94 q95 q96 q1 q2 q3 q4 q5 q6 q7 q8 .. .. .. .. .. .. .. ..
1995 jul 17 13 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h in this instance, synchronization of q-channel frames must be maintained by the microcontroller. it is recommended to read decoded q-channel data in groups of 12 bytes otherwise synchronization of subcode frames may be lost quickly. again, the data transfer is supported by the signal at pin udavail. this time it goes low when there is at least one full frame (12 bytes) of q-channel data in the buffer, and goes high again, when less than 12 bytes are in the buffer. this is illustrated in fig.4. an initial synchronization can be obtained by clearing the buffer via the control register, then start counting bytes modulo 12. again, the lsb is sent first on the user interface, i.e. the first byte of a q-channel frame will be output as follows: 1. bit sent = q8. 2. bit sent = q7. 3. bit sent = q6. 4. bit sent = q5. 5. bit sent = q4. 6. bit sent = q3. 7. bit sent = q2. 8. bit sent = q1. writing to the buffer is disabled when the fifo is full. it is re-enabled when there is at least 1 byte free. any data overrun condition will be flagged as an error in the status register. when this has occurred, the appropriate strategy for data handling is decided by the microcontroller. it can, for example, clear the buffer via the control register, thereby discarding all remaining data, or it can start reading data rapidly. clearing the buffer turns udavail high. the response to reading data is the same as described previously, depending on the mode of reception, i.e. q-channel decoding or normal message protocol. for the period that the user data register is selected, the microcontroller has to poll udavail each time after reading one byte in normal mode, or 12 bytes in q-channel mode. possible actions by the microcontroller are as follows: if udavail = 0: reading the next byte in normal mode or the next 12 bytes in q-channel mode. if udavail = 1: either wait until udavail goes low and continue reading user data byte(s), or write data, read other data or deselect the TDA1315h by foreign addressing. C remark: it is allowed to address the TDA1315h for reading user data again when udavail is still high, but it is forbidden to apply clock pulses until udavail has gone low. remark: whenever the buffer is empty (udavail = 1), normally zeroes will be read, even when the microcontroller tries to read more bytes. doing so, however, poses the risk of reading not all zeroes. in this event new data is stored in the buffer during reading, thereby losing synchronization. to assure correct information will be read, the microcontroller should perform an addressing sequence (not necessarily to the TDA1315h), whenever an udavail high is detected before reading further. transmit mode user data bits are supplied by the microcontroller in the general message format only, q-channel encoding is not available in the TDA1315h. again, udavail can be used to synchronize transfers. it goes high, when the buffer contains at least 112 bytes, and goes low only when there are no more than 16 bytes in the buffer. this is illustrated in fig.5. thus, after udavail has gone low, the microcontroller can write a full cd subcode frame (96 data bytes plus 2 synchronization bytes) to the buffer without needing to poll the state of pin udavail. in the event that no data are available in the buffer, the user data bits in the iec output signal will be set to zero. should the microcontroller attempt to write more data than the buffer can hold, writing will be disabled and the data overrun bit set in the status register. any bytes that have been transferred but not written into the buffer are lost. four zero bits will be inserted automatically between user data bytes (information units). the gap between messages can be achieved by writing a single byte containing all zeroes to the buffer. u ser interface the user interface is an interface between the data processing sections of the TDA1315h and the user. the basic mode of operation (control by a host or stand-alone operation) is selected by pin ctrlmode. in the host mode, all data, control and status information is, in principle, exchanged with a microcontroller although the device configuration can also be changed by pin control. up to 2 TDA1315hs can be used on the same user interface by setting different device addresses via the laddr pin. in the stand-alone mode (receive only), no microcontroller is needed because important information is brought out to pins fs32, fs44 and fs48, being an indication of sample frequency, copyright protection (copy) (see chapter references[2]) and use of pre-emphasis (deem).
1995 jul 17 14 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h stand-alone mode in this mode, the TDA1315h is automatically configured as a receiver. the configuration, i.e., the mode of operation of the device, is determined by pins ctrlmode, iecsel, iecoen, clksel, i 2 ssel and i 2 soen. because all of the pins have internal pull-up resistors, the default configuration can be changed by pulling a pin low. the output signals listed below are provided from the channel status. however, all of them are switched off when the pll is not locked. this includes the situation where no iec input signal is available: sample frequency is 32 khz (pin fs32) sample frequency is 44.1 khz (pin fs44) sample frequency is 48 khz (pin fs48) copyright status bit (pin copy) pre-emphasis bit (pin deem). as there will be no output signals from the channel status in the event that non-consumer iec signals are received, the i 2 s-bus output will still output data in 24 bits format. an led can be connected to pin chmode to provide an indication of such a situation. host mode in this mode, the exchange of data and control information between the TDA1315h and a microcontroller is via a serial hardware interface, which comprises the following pins: ldata to microcontroller interface data line. lclk to microcontroller interface clock line. lmode to microcontroller interface mode line. laddr to microcontroller interface address switch. two different modes of operation can be distinguished: 1. addressing mode. 2. data transfer mode. the addressing mode is used to select a device for subsequent data transfer and to define the direction of that transfer as well as the source or destination registers. the addressing mode is characterized by lmode being low and a burst of 8 clock pulses at lclk, accompanied by 8 data bits. the fundamental timing is illustrated in fig.6. data bits 0 to 1 indicate the type of subsequent data transfer as given in table 7. the direction of the channel status and user data transfers depends on the transmit/receive mode. data bits 2 to 7 represent a 6-bit device address, with bit 7 being the msb and bit 2 the lsb. the address of the TDA1315h is 000001 (laddr = 0) or 000010 (laddr = 1). should the TDA1315h receive a different address, it will immediately 3-state the ldata pin and deselect its microcontroller interface logic. a dummy address of 000000 is defined for the deselection of all devices that are connected to the serial microcontroller bus. fig.3 user data handshake.
1995 jul 17 15 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h fig.4 q-channel handshake. fig.5 transmit mode handshake. fig.6 addressing mode timing.
1995 jul 17 16 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h table 7 selection of data exchange in the data transfer mode, the microcontroller exchanges data with the TDA1315h after it has addressed the device and defined the type of data for that exchange. the selection remains active until the TDA1315h receives a new type of data or is deselected. the fundamental timing of data transfers is illustrated in fig.7, where ldata denotes the data from the TDA1315h to the microcontroller (ldata read). the timing for the opposite direction is essentially the same as in the addressing mode (ldata write). bit 1 bit 0 transfer direction 0 0 channel status input/output 0 1 user data input/output 1 0 control input 1 1 status output fig.7 data transfer mode timing. all transfers are bytewise, i.e. they are based on groups of 8 bits. data will be stored in the TDA1315h after the eighth bit of each byte has been received. it is possible to read only the first byte of the channel status and of the TDA1315h status register. a multi-byte transfer is illustrated in fig.8. as some other devices, which are expected to connect to the same microcontroller bus lines, require an indication of when 8 bits have been transferred, a so-called halt mode has been defined. it is characterized by the following conditions: lmode = low, ldata = 3-state and lclk = high. the TDA1315h does not need this mode to distinguish one byte from the next, however, it will not make any difference when this occurs. when not used, there is no need to increase the time between the last lclk pulse of a byte and the first lclk pulse of the next byte.
1995 jul 17 17 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h fig.8 multi-byte transfer. daio control under microcontroller control, there is also a transmit mode available. therefore, setting the device configuration is slightly different from the stand-alone mode. most functions or modes can be set by pins or by the control register or by both. negative logic is used to implement this or function. the initial setting of the control register is all ones. for most functions, the TDA1315h can be configured only by pins, as explained for the stand-alone mode. the principle of this type of control is illustrated in fig.9. however, for changing clksel, i 2 ssel and the receive/transmit mode, there is a configuration register, which is updated only by an externally supplied strobe signal. this allows synchronization with other ics. at pin ldata, control information is first entered serially into a shift register and then latched in the control register when complete. the bits of the second byte (6 are used) of this register are internally ored with their corresponding pins, so that either a low or a logic 0 bit will result in a logic 0 state (active low). these combined states are then entered in the status register. the resulting clksel and i 2 ssel information is supplied to the configuration register, i.e. these bits will only be executed in the TDA1315h, together with the receive/transmit bit, after a strobe has been received. this applies to the host mode. in the stand-alone mode, the configuration register is transparent and any configuration changes are executed immediately. when the TDA1315h status is read, the contents of the status register are output serially at pin ldata, thereby reflecting the or combination of configuration control bits and associated pins (negative logic). the microcontroller is thereby able to determine whether a pin is open-circuit or tied to ground. when a strobe is applied in the receive mode (to switch to transmit mode), the outputs ws and sck are disabled one or two system clock periods after the rising edge of strobe. at the same time sysclko will be forced low and will be disabled one system clock later. in the transmit mode it is possible to set the receive/transmit bit to zero and then poll the locking status of the TDA1315h and wait with a strobe until the TDA1315h is in-lock. this method can be used to check whether there is an iec source, since the TDA1315h will not lock without one. it should be noted that the locking status bit and the unlock pin are only valid, i.e. its value has a meaning, when you are in either the receive mode or the receive/transmit bit is set to zero in the transmit mode. when the configuration is changed to the receive mode, ws, sck, invalid and sysclko outputs are enabled one or two system clock periods after the falling edge of strobe. sysclko will always be initially low, for a short time, and then pulses will appear always starting with the rising edge. in general ws and sck outputs are always enabled/disabled simultaneously. output invalid will only be enabled when sd, ws and sck are all enabled. the mode timing is illustrated in fig.10. the control register consists of two bytes. the meaning of the control register bits is given in tables 8 and 9. all bits default to a logic high state after a reset to the TDA1315h. this requires a reset for proper initialization when ctrlmode is changed after power-up. the lsb (bit 0) is always transferred first.
1995 jul 17 18 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h fig.9 mode control. table 8 first byte of control register note 1. bit 4 is reset to high after the TDA1315h has cleared the buffer and has either caused udavail to go high in the receive mode or low in the transmit mode. bit description function 0 transmit/receive mode 0 = receive 1 = transmit 1 decode subcode q-channel 0 = enable 1 = disable 3 and 2 number of bits to transfer 00 = 16 bits 01 = 18 bits 10 = 20 bits 11 = 24 bits 4 (1) clear user data buffer 0 = clear 1 = leave as is 5 reserved 0 = unde?ned 1 = default 6 reserved 0 = unde?ned 1 = default 7 reserved 0 = unde?ned 1 = default table 9 second byte of control register bit description function 0 audio mute 0 = enabled 1 = disabled 1 iec output enable 0 = enabled 1 = disabled 2 select iec input 0 = ttl level 1 = high sensitivity 3i 2 s-bus output enable 0 = enabled 1 = disabled 4 select i 2 s-bus source 0 = sdaux 1=sd 5 select clock frequency 0 = 384f s 1 = 256f s 6 reserved 0 = unde?ned 1 = default 7 reserved 0 = unde?ned 1 = default
1995 jul 17 19 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h fig.10 mode switching and timing strobe input.
1995 jul 17 20 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h status the status register consists of two bytes. a description of the status register bits is given in tables 10 and 11. after a reset all bits in the status register will be one. the various error conditions of the TDA1315h are reflected in bits 0 to 6 of the first byte. the error bits are set (low) when the corresponding error conditions occur, they are reset (high) only after the register has been read by the microcontroller. bit 7 reflects the active transmit/receive state. it is updated after the TDA1315h configuration, as determined by bit 0 of the first control register byte, has been changed. this allows verification of the mode change to, for example, release a mute signal after a successful change. table 10 first byte of status register bit description function 0 channel status mode 0 = professional 1 = consumer 1 pll lock condition 0 = not locked 1 = locked 2 validity ?ag 0 = error 1 = no error 3 parity check 0 = error 1 = no error 4 biphase violation 0 = error 1 = no error 5 user data overrun 0 = error 1 = no error 6 channel status check 0 = change 1 = no change 7 direction of data 0 = receive 1 = transmit table 11 second byte of status register note 1. bits 6 and 7 in the second byte of the status register contain the inversion of bits 7 and 6, respectively, of the channel status, which are used as mode bits. reset and standby mode figure 11 illustrates the timing for the toggling between normal and standby mode. in figs 11 and 12, when activating pd or reset, 0 ns can be taken for t on:osc when the oscillator is running (e.g. receive mode). the TDA1315h uses its internal oscillator for the reset and standby function. this means that it is not necessary, in any mode, to apply a clock at the sysclki input for the TDA1315h to perform the reset or standby function. for resetting the TDA1315h only a small pulse is necessary at the reset input. the device then automatically starts the oscillator (in the event that it is not running). the system will then do a synchronous reset (internally) during approximately 3 internal clock periods. this t reset starts after the falling edge of reset or when the oscillator has started, whichever occurs last. only when this resetting has been accomplished will the external pin programming (e.g. clksel, i 2 soen etc.) be read by the TDA1315h. the TDA1315h is then ready for use. bit description function 0 audio mute 0 = enabled 1 = disabled 1 iec output enable 0 = enabled 1 = disabled 2 select iec input 0 = ttl level 1 = high sensitivity 3i 2 s-bus output enable 0 = enabled 1 = disabled 4 select i 2 s-bus source 0 = sdaux 1 = iec or cd 5 select clock frequency 0 = 384f s 1 = 256f s 6 (1) channel status (bit 7) 0 = bit 7 set 1 = bit 7 reset 7 (1) inverse mode bit (bit 6) 0 = bit 6 set 1 = bit 6 reset
1995 jul 17 21 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h fig.11 standby mode timing. fig.12 reset timing.
1995 jul 17 22 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. in all events and, also, when applied voltages are below - 0.5 v or above v dd + 0.5 v this current limitation should be taken into account to prevent device damage. 2. human body model: pins 25, 27, 30, 31 and 35 to 37 = 1500 v; r = 1.5 k w ; c = 100 pf; 3 zaps positive and 3 zaps negative. 3. machine model: r = 25 w ; c = 200 pf; l = 0.5 m a; 3 zaps positive and 3 zaps negative. handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage (pins 3, 17 and 42) - 0.5 +6.5 v i dd supply current per pin (pins 3, 17 and 42) - 50 ma v all voltage supplied to all pins without current limitations - 0.5 v dd + 0.5 v i i/o input/output current on any pin except supply pins and pins 8, 12 to 16, 29 and 40 note 1 - 10 ma i i input current pins 12 to 16 and 29 v o > v dd + 0.5 v; output disabled; note 1 - 10 ma i i/o input/output current pins 12 to 16 and 29 v o < v dd + 0.5 v; note 1 - 20 ma i 8 input/output current pin 8 note 1 - 60 ma i 40 input/output current pin 40 note 1 - 80 ma p tot total power dissipation - 500 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 20 +70 c v es electrostatic handling note 2 - 2000 +2000 v note 3 - 200 +200 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 80 k/w
1995 jul 17 23 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h characteristics v ddd1 =v ddd2 =v dda = 3.4 to 5.5 v; t amb - 20 to +70 c; rise, fall, set-up and hold times are speci?ed between 10% and 90% of full amplitude; delays between 50%; times to and from 3-state with r l = 1.5 k w to 1 2 v dd ; typical values are valid at the typical supply voltage of 5 v unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage v ddd =v dda 3.4 5.0 5.5 v i ddd digital supply current pd = 1; t amb =25 c -- 10 m a i dda analog supply current pd = 1; t amb =25 c -- 10 m a t he following parameters are typical for receive mode ; all outputs enabled ( not loaded ); t amb =25 c; v dd =5v i ddd digital supply current f s = 48 khz; clksel = 0 - 13 - ma i dda analog supply current f s = 48 khz; clksel = 0; when iecin1 input is used - 2.6 - ma p tot total power dissipation f s = 48 khz; clksel = 0; when iecin1 input is used - 80 - mw ttl input switching levels (without schmitt-trigger) a pplicable to peripheral types : ipp04, iup04, idp04, iof24 and iod24 v il low level input voltage v dd = 3.4 v -- 0.5 v v dd = 4.5 v -- 0.8 v v dd = 5.5 v -- 0.8 v v ih high level input voltage v dd = 3.4 v 1.5 -- v v dd = 4.5 v 2.0 -- v v dd = 5.5 v 2.0 -- v ttl input thresholds (with schmitt-trigger) a pplicable to peripheral types : ipp09, idp09 and iof29 v thl negative-going threshold v dd = 3.4 v 0.3 -- v v dd = 4.5 v 0.6 -- v v dd = 5.5 v 0.6 -- v v tlh positive-going threshold v dd = 3.4 v -- 1.9 v v dd = 4.5 v -- 2.4 v v dd = 5.5 v -- 2.4 v v hys hysteresis voltage v dd = 3.4 v - 0.6 - v v dd = 4.5 v - 0.6 - v v dd = 5.5 v - 0.8 - v input pull-up and pull-down resistor values; note 1 a pplicable to peripheral types : iup04, idp04, idp09 and iod24 r pull pull-up or pull-down resistors v dd = 3.4 v 32 - 203 k w v dd = 4.5 v 21 - 134 k w v dd = 5.5 v 17 - 104 k w
1995 jul 17 24 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h outputs sink and source capabilities a pplicable to peripheral types : opf23, iof24, iod24, and iof29 (2 ma outputs ) v ol low level output voltage v dd = 3.4 v; i o = 1.5 ma -- 0.5 v v dd = 4.5 v; i o =2ma -- 0.5 v v dd = 5.5 v; i o = 2.25 ma -- 0.5 v v oh high level output voltage v dd = 3.4 v; i o = - 1.5 ma 2.9 -- v v dd = 4.5 v; i o = - 2 ma 4.0 -- v v dd = 5.5 v; i o = - 2.25 ma 5.0 -- v a pplicable to peripheral type : opp41a (4 ma output ) v ol low level output voltage v dd = 3.4 v; i o =3ma -- 0.5 v v dd = 4.5 v; i o =4ma -- 0.5 v v dd = 5.5 v; i o = 4.5 ma -- 0.5 v a pplicable to peripheral type : opfh3 (12 ma output ) v ol low level output voltage v dd = 3.4 v; i o =9ma -- 0.5 v v dd = 4.5 v; i o =12ma -- 0.5 v v dd = 5.5 v; i o = 13.5 ma -- 0.5 v v oh high level output voltage v dd = 3.4 v; i o = - 9 ma 2.9 -- v v dd = 4.5 v; i o = - 12 ma 4.0 -- v v dd = 5.5 v; i o = - 13.5 ma 5.0 -- v a pplicable to peripheral type : opfa3 (16 ma output ) v ol low level output voltage v dd = 3.4 v; i o =12ma -- 0.5 v v dd = 4.5 v; i o =16ma -- 0.5 v v dd = 5.5 v; i o =18ma -- 0.5 v v oh high level output voltage v dd = 3.4 v; i o = - 12 ma 2.9 -- v v dd = 4.5 v; i o = - 16 ma 4.0 -- v v dd = 5.5 v; i o = - 18 ma 5.0 -- v input and 3-state (off state) leakage currents a pplicable to peripheral types : ipp04 and ipp09 | i li | input leakage current v i = 0 or 5.5 v; v dd = 5.5 v -- 1 m a a pplicable to peripheral types : opf23, opfh3, opfa3, opp41a, iof24 and iof29 | i oz | 3-state leakage current v o = 0 or 5.5 v; v dd = 5.5 v -- 5 m a iec interface; note 2 ; (for timing see chapter references, item 1) ieco ( pin 8) t diec output delay with respect to iecinx receive mode 2t c - 3t c +50 ns symbol parameter conditions min. typ. max. unit
1995 jul 17 25 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h iecin1 ( pin 5) v i(p-p) ac input voltage (peak-to-peak value) 0.2 - v dd v i i input current v i = 0 or 5 v; v dd =5v - 550 -m a v bias dc bias voltage - 0.5v dd - v i 2 s-bus interface; (for timing see chapter references, item 3) sd input / output ( pin 35) t dsdaux output delay with respect to sdaux -- 50 ns microcontroller interface (see figs 6 and 7) t lclk period t c +50 -- ns t hc lclk high period 25 -- ns t lc lclk low period 25 -- ns t su;ad laddr set-up time 25 -- ns t hd;ad laddr hold time 25 -- ns t su;ma lmode set-up time addressing mode 1 2 (t c + 50) -- ns t hd;ma lmode hold time addressing mode 1 2 (t c + 50) -- ns t su;mt lmode set-up time halt mode 25 -- ns t hd;mt lmode hold time halt mode 25 -- ns t su;da ldata set-up time write and addressing mode 25 -- ns t hd;da ldata hold time write and addressing mode 25 -- ns t en;dt ldata enable time data read mode -- 50 ns t hd;dt ldata hold time data read mode; note 3 1 2 t c - t c +50 ns t 3dt ldata disable time data read mode -- 50 ns t halt lmode halt time 0 -- ns mode switching and strobe (see fig.10) t h;sb strobe high time 3t c +50 -- ns t l;sb strobe low time 3t c +50 -- ns t su;sb set-up time before strobe for pins or bits - t c +50 -- ns t hd;sb hold time after strobe for pins or bits 2t c +50 -- ns t dbit delay lclk to internal bit control register 2t c - 3t c +50 ns t en;sd sd enable time t c - 2t c +50 ns t 3sd sd and invalid disable time -- t c +50 ns t en;ws ws, sck and invalid enable time t c - 2t c +50 ns t 3ws ws and sck disable time t c - 2t c +50 ns t en;co sysclko enable time t c - 2t c +50 ns symbol parameter conditions min. typ. max. unit
1995 jul 17 26 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h t 3co sysclko disable time 2t c - 3t c +50 ns t le;co sysclko low time when enabled 1 2 t s - 1.5t s +50 ns t ld;co sysclko low time when disabled t c - t s - t c +50 ns t hd;ci sysclki hold time 3t c +50 -- ns t on;osc oscillator start-up time c ref in m f; note 4 0 - 1 10 c ref s t off;osc oscillator switch-off time 2t c - 3t c +50 ns standby mode (see fig.11) t 3op outputs disable time -- t c +50 ns t en;op outputs enable time -- t c +50 ns t 3cr sysclko disable time receive mode t c - 2t c +50 ns t en;cr sysclko enable time receive mode -- t c +50 ns reset (see fig.12) t hr reset high time 25 -- ns t reset internal reset time -- 2 m s clock and timing (pins sysclki and sysclko) d sysclki input clock duty factor 30 50 70 % d sysclko output clock duty factor 45 50 55 % d t/t sysclko output clock jitter d v dda < 10 m v - 50 10 - 6 - k ol vco conversion gain rc ?l to sysclko; clksel = 1 - 225 10 6 - rad/s/v k oh vco conversion gain rc ?l to sysclko; clksel = 0 - 250 10 6 - rad/s/v 2f rl vco frequency tuning range at sysclko; clksel = 1 - 16 - mhz 2f rh vco frequency tuning range at sysclko; clksel = 0 - 22 - mhz f cl vco centre frequency at sysclko; rc ?l =v ref ; clksel = 1 - 12.5 - mhz f ch vco centre frequency at sysclko; rc ?l =v ref ; clksel = 0 - 19 - mhz v ref output ( pin 2) v ref output reference voltage - 2.1 - v i ref output reference current v ref =0v - 28 -m a rc ?l input ( pin 1) v trl input tuning voltage f s = 32 to 48 khz; clksel = 1 - 100 - mv v trh input tuning voltage f s = 32 to 48 khz; clksel = 0 - 150 - mv | i li | input leakage current v i = 0 or 5.5 v; v dd = 5.5 v; testb = 1 -- 1 m a symbol parameter conditions min. typ. max. unit
1995 jul 17 27 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h notes 1. pull-up specified at input to v ss , pull-down specified at input to v dd . 2. most timing specifications are related to clock periods. two basic periods are of importance: a) t c , this is the internal clock period of the TDA1315h being 1 128 f s seconds. b) t s , this is the system clock period such as sysclki or sysclko, being 1 256 f s or 1 384 f s seconds. c) it should be noted that in the receive mode clock frequencies are only reliable when the TDA1315h is in-lock. 3. in the transmit mode, when sysclki is 384f s and 30% or 70% duty cycle: t hd;dt is 0.43t c minimum. 4. this time strongly depends on the external decoupling capacitor connected to v ref (pin 2). when the capacitor is initially empty, it must first be charged before the oscillator can start. 5. internally this resistor will be connected between rc fil and v ref , when there is no signal on the selected iec input in receive mode, or when the oscillator is turned off. this is to prevent the oscillator to drift to extreme low or high frequencies. see also chapter characteristicswith regards to f oclk(l) and f oclk(u) . 6. these figures are theoretical limits for the TDA1315h. in the application, the maximum frequencies at f s = 48 khz will be fixed. consequently f iclk = 12.288 mhz (clksel = 1) and f iclk = 18.432 mhz (clksel = 0). 7. these frequencies mean that the TDA1315h is guaranteed to lock in the range f s = 31.5 to 48.5 khz over the whole supply voltage range and specified temperature range. 8. these are the limit frequencies that the internal oscillator may reach under extreme conditions when the vco input (pin rc fil ) would be controlled far beyond its normal tuning range. an internal resistor however, prevents that these frequencies can be reached when there is no signal to lock-on to. see also chapter characteristics regarding r tr . quality specification in accordance with snw-fq-611e . the number of this quality specification can be found in the quality reference pocketbook . the pocketbook can be ordered using the code 9398 510 34011. r tr transmission-gate resistor v ref = 2.1 v; v dd =5v; note 5 - 1 - m w rc int output ( pin 44) c o parallel output capacitance - 5 - pf i ch(fr) output charge current frequency detector loop - 12 -m a i ch(ph) output charge current phase detector loop - 24 -m a sysclki input ( pin 39); transmit mode ;v dd = 3.4 to 5.5 v f iclk input clock frequency clksel = 1; note 6 -- 16 (6) mhz clksel = 0; note 6 -- 24 (6) mhz sysclko output ( pin 40); receive mode ;v dd = 3.4 to 5.5 v f oclk(l) output clock frequency lower limit oscillator clksel = 1 2 (8) - 8.06 (7) mhz clksel = 0 4 (8) - 12.09 (7) mhz f oclk(u) output clock frequency upper limit oscillator clksel = 1 12.42 (7) - 26 (8) mhz clksel = 0 18.63 (7) - 37 (8) mhz symbol parameter conditions min. typ. max. unit
1995 jul 17 28 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h test and application information figures 13 to 15 indicate typical systems environment of the TDA1315h. they are intended to give examples of which external blocks may be added to compose a system for particular requirements. the loop filter configuration and values in the examples meet the requirements for mid-end and high-end audio applications. test information table 12 test pin functions table 13 implemented test scan chains test pin description testa = 0 normal application operation testa = 1 test mode i.e. system clock equals sysclki testb = 0 normal mode when testa = 1 testb = 1 scan mode when testa = 1; high-ohmic resistor between rc ?l and v ref pins always disabled testc = 0 normal operation testc = 1 chmode equals system clock; ieco equals iecin1 slicer output; ram test enabled scan number length (bits) scan input output active edge of sysclki 1 54 iecsel fs32 negative 2 54 iecoen fs44 negative 3 54 laddr fs48 negative 4 54 mute copy negative 5 53 lmode chmode negative 6 53 strobe udavail negative 751i 2 ssel deem negative 8 31 clksel unlock positive
1995 jul 17 29 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h stand alone application (receive only) a very simple implementation of the stand-alone application is illustrated in fig.13. in simple terms, it is an iec-to-analog converter. the iec signal is input via a shielded cable and enters the TDA1315h via its high-sensitivity input. the audio output is supplied to a dac via the enabled i 2 s-bus port, the deem output can be used to switch a de-emphasis network in and out of the signal path. the system clock frequency can be selected and is available should any digital filters in the dac block require such a clock. the sample frequency of the received signal together with any out-of-lock condition of the phase-locked loop and the presence of a professional mode iec signal can be displayed with leds. fig.13 simple stand-alone application. when in a system both iecin1 and iecin0 inputs are used, the signal that is applied to the iecin0 input must be kept away from the iecin1 input on the printed-circuit board. steep slopes of the iecin0 input can be seen by the sensitive adjacent iecin1 input. an extra capaci tance parallel to the 75 w resistor, close to the TDA1315h, can help reduce the crosstalk if required. a suitable value is 180 pf.
1995 jul 17 30 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h microcontroller based application (receive and/or transmit) the microcontroller-based application is illustrated in fig.14. functional blocks are shown for both the receive and the transmit mode. here, the iec signal is input via an optical fiber link and an associated optocoupler and enters the TDA1315h at its ttl-level input. the i 2 s-bus output signal is applied to a digital signal processing module, which may contain signal processors, dacs, a recording device etc. an adc can be an optional source for that module. as the microcontroller can obtain all status information and data via the serial bus, it will provide display information and also will control the whole system, including the receive/transmit switch. for simplicity reasons, pin-based mode selection is not shown in this diagram. in the transmit mode, both system clock and i 2 s-bus timing are derived from a central timing block. the iec output signal feeds an optical fiber link via a suitable optocoupler. concerning the wide supply voltage range of the TDA1315h, it is not possible to have a transformer-coupled iec output that fulfils the iec 958 standard over the full supply voltage range. the output will have an amplitude of 0.5 v (p-p) with a tolerance of 20%. fig.14 microcontroller-based application.
1995 jul 17 31 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h transmit mode only application (also possible without microcontroller) in fig.15 an example is given, how the TDA1315h can be operated as a transmitter without microcontroller. when the ctrlmode pin is low, a reset applied to theTDA1315h will result in a default transmit mode. when the user is not interested in sending non-default channel status data (zeros) or user data, it remains always possible to encode audio data at the i 2 s bus to the iec output. when no microcontroller is used, the TDA1315h will remain fully pin programmable when strobe is connected to supply permanently. when the receive mode is not used, a dedicated loop-filter for the pll is not necessary. however, for correct operation the TDA1315h does need a functional oscillator. the minimum configuration is defined by keeping pin 44 (rc int output) floating and connecting pin 1 (rc fil input) to pin 2 (v ref output). for the resetting and standby functions the oscillator will operate correctly. fig.15 transmit-mode-only application.
1995 jul 17 32 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h references 1. digital audio interface , first edition 1989-03, international standard iec 958 . 2. digital audio interface for domestic use , philips/sony, september 1983. 3. i 2 s-bus specification , release 2-86, philips export b.v., order number 9398 332 10011. 4. amendment to document iec 958: digital audio interface , project number. 84.11.02107. 5. saa7310, development data sheet , philips semiconductors, october 1987, order number 9397 153 90142.
1995 jul 17 33 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1995 jul 17 34 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h soldering qfp introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference manual (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 c.
1995 jul 17 35 philips semiconductors product speci?cation digital audio input/output circuit (daio) TDA1315h definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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(0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040)783749, fax. (040)788399 (from 10-10-1995: tel. (040)2783749, fax. (040)2788399) new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 (from 10-10-1995: +31-40-2724825) scd41 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/1500/05/pp36 date of release: 1995 jul 17 document order number: 9397 750 00217

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